The present invention relates generally to improvements which increase the linearity of pipeline ADCs (analog-to-digital converters), and more particularly to improvements which substantially reduce the number of “next stage comparators” in the pipeline ADC. The invention relates yet more particularly to improvements which also reduce the amount of integrated circuit chip area and power dissipation compared to that of prior pipeline ADCs.
A pipeline ADC includes a sequence of pipeline ADC “stages”. FIG. 1 shows a single conventional pipeline ADC stage 1 wherein an analog input signal VIN is applied by conductor 7 to the input of a sub-ADC 8 and to the (+) input of a residue amplifier 11. Sub-ADC 8 typically is implemented by means of a flash ADC. The digital output of sub-ADC 8 is applied to the input of a conventional multiplier DAC (MDAC) 9, the output of which is applied to the (−) input of residue amplifier 11, which produces a residue voltage VRES on conductor 12. A residue plot for pipeline ADC stage 1 is shown in FIG. 2. (A flash ADC typically includes a string of equal resistors connected in series as a voltage divider between a pair of reference voltages to generate individual reference voltages on various circuit nodes or tap points between the respective resistors. Each individual reference voltage may be connected to the (+) input of a corresponding comparator, and the (−) input of each comparator may be connected to an analog input voltage. The comparator outputs provide a digital representation of the analog input voltage.)
In the operation of a conventional pipeline ADC there is just one amplification phase, which is called a “hold” phase because it is accomplished by means of a sample/hold circuit wherein VIN is sampled during a sample phase and amplified during a hold phase. The accuracy with which the sampling and amplification needs to be performed depends on the resolution of the pipeline ADC.
Various errors generated in the known pipeline ADCs cause nonlinear operation thereof. One source of error is random input offset voltages of the flash comparators of the various stages. Another source of error is random input-referred input offset voltages of the residue amplifiers of the various stages. Yet another, error is due to variations in the series-connected resistors of the flash ADCs.
The sub-ADC 8 of FIG. 1 typically generates m bits of sub-ADC code, plus a redundancy bit, if needed, to allow correction of some of the above errors. A known technique for eliminating the effect of the foregoing sources of error on the linearity of a pipeline ADC is referred to as providing “redundancy” in the various pipeline ADC stages. The redundancy is accomplished by providing sub-ADCs with a larger number of bits than the number of bits to be resolved by the various stages, respectively. For example, addition of one or more redundancy bits to the sub-ADC in each pipeline ADC stage except the first stage introduces redundancy, and the redundancy is effective to correct sub-ADC errors generated in the previous stage. For example, if the sub-ADC of a stage of the pipeline ADC is required to resolve 3 bits, then providing a fourth bit introduces redundancy by providing one additional bit of resolution in the sub-ADC of the next pipeline ADC stage. The redundancy provides additional range for the swing of the residue amplifier output voltage, and that additional range is used to correct for the error generated in the previous stage. However, the redundancy bit is not used as part of the sub-ADC code generated by that sub-ADC. (In an ideal circuit, the sub-ADC would not have any error so no redundancy bit would be required.)
An ideal pipeline ADC stage that resolves n effective bits has an n-bit sub-ADC and therefore 2n comparators in the sub-ADC. The gain of the residue amplifier of the stage also needs to be 2n. However, in the presence of redundancy of 1-bit, the sub-ADC resolution has to be increased to (n+1) bits and therefore the number of comparators has to be increased to 2n+1. The residue amplifier gain still remains equal to 2n. In other words, the gain of the residue amplifier is reduced by a factor of ½ as compared to the resolution of the sub-ADC. Since the gain of the residue amplifier is reduced by half, its output voltage VRES then will have a dynamic range that spans ±Vref/2, rather than ±Vref as in the ideal case wherein there are no errors in the sub-ADC comparators. The extra dynamic range between −Vref and −Vref/2 and between +Vref/2 and +Vref corresponds to be the actual “redundancy” that is “used” to correct errors in the sub-ADC comparators of the pipeline ADC stage. In summary, the pipeline ADC stage with redundancy requires double the number of comparators in the sub-ADC as compared to an ideal pipeline ADC stage.
The ideal pipeline ADC stage which has no errors from the sub-ADC requires ideal comparators that have “zero” input-referred offset. Since this is not achievable in practice, redundancy is added, as explained above, in the conventional pipeline ADC stage. Redundancy makes the design of the sub-ADC feasible, but the comparator input offset specification is still “tight” enough to necessitate use of a preamplifier stage in each of the comparators to amplify the comparator input signal before it is passed on to a latch that makes the comparator decision. The preamplifier stage in each comparator requires undesirably large amounts of additional chip area and power dissipation. This limitation is especially large for ADCs having higher than 10-bit resolution.
A “cost” or drawback of using a redundancy bit in a pipeline ADC stage is that the number of flash ADC comparators in the pipeline ADC stage must be doubled.
Since the residue voltage VRES produced by the residue amplifier of each pipeline ADC stage needs to be able to swing accurately between ±Vref, the first stage (or first few stages) of a high-resolution pipeline ADC requires the residue amplifier of each such stage to have high DC gain and high bandwidth. Unfortunately, this complicates the design of the residue amplifier of each pipeline ADC stage. A technique that has been used to solve the design complications is referred to as “reference scaling”, and is disclosed in commonly assigned U.S. Pat. No. 7,161,521 entitled “Multi-Stage Analog to Digital Converter Architecture” issued Jan. 9, 2007 to Nandi et al.; this patent is entirely incorporated herein by reference. In the reference scaling technique, the gain of the residue amplifier of the flash ADC of each pipeline ADC stage following the first stage is reduced further by a factor of 2. The gain of the residue amplifier for a pipeline ADC stage that resolves n “effective” bits is made equal to 2n−1, instead of 2n. In this way, the output swing of the residue amplifier is reduced by a factor of 2. In the presence of sub-ADC errors, the maximum output swing of the residue amplifier is limited to +/−Vref/2, as compared to +/−Vref in case of the conventional stage. (The output swing of an ideal pipeline stage is +/−Vref/4 when the reference scaling technique is used, as opposed to +/−Vref/2 for a conventional stage.)
When reference scaling is used, the residue amplifier output voltage has to swing between ±Vref/2. This allows design of the residue amplifier to be substantially simplified. However, a disadvantage of reference scaling is that the input offset specification requirements are substantially increased for the flash ADC comparators in the sub-ADC of the next pipeline ADC stage. That makes it necessary to use substantially larger, substantially more power-consuming comparator circuitry. Reference scaling reduces residue amplifier output voltage swing, and also reduces the DC gain and bandwidth requirements of the residue amplifier. Unfortunately, this tightens the input offset specification requirement of the flash ADC comparators of the following stage. The next pipeline ADC stage requires 2m+1 comparators to span an input range from −Vref/2 to +Vref/2, where m is the number of bits to be resolved the by that pipeline ADC stage. In the absence of the previously mentioned error sources, only 2m comparators spanning −Vref/2 to +Vref/2 would be needed. For example, a 12-bit ADC having four 3-bit pipeline ADC stages arranged in a 3-3-3-3 configuration would require a total of 56 flash ADC comparators. If reference scaling is used, the cost and power dissipation of the pipeline ADC would be substantially increased because each flash ADC comparator would need to be composed of substantially larger, substantially more power-consuming circuitry. Although the reference scaling architecture solves the previously mentioned problems caused by large residue amplifier output voltage swings, reference scaling does not change the requirement of doubling the number of flash ADC comparators if redundancy bits are introduced.
FIG. 3 is a copy of FIG. 7A of above-mentioned U.S. Pat. No. 7,161,521, and illustrates a conventional flash ADC 8 which may be used as the sub-ADC in block 8 of FIG. 1. Flash ADC 8 includes comparators 710-1 through 710-2q+1 are connected to comparators 710-1 and 2q+2+1 equal resistors 730A-730Z. Flash ADC 8 is assumed to be generating a q-bit sub-code based on a differential reference input REFP-REFM which is equal to Vref. Resistors 730A-730Z operate as a resistor ladder network which divides the foregoing reference voltage Vref into equal voltage steps. The resistor ladder network generates 2q+2 levels, the 2q+1 level middle half of which are connected to the (+) inputs of comparators 710-1 through 710-2q+2. Note that one-fourth of the generated 2q+2 levels located on each side, respectively, of the middle half are not connected to any comparator inputs. (It should be understood that 2q comparators and 2q+1 resistors, would be required in the case of a single-ended implementation.) Comparators 710-1 through 710-2q+1 provide a q-bit sub-code by comparing the differential analog input signal InpP-InpM with the corresponding 2q+1 middle half levels generated by the resistor ladder network. As a result, the differential analog input signal InpP-InpM is compared within the dynamic range of REFP/2 and REFM/2. The output of the flash ADC comparators represents a sub-code generated by sub-ADC 8.
There is an unmet need for an accurate, linear pipeline ADC which requires substantially less integrated circuit chip area and power dissipation than prior pipeline ADCs that have otherwise essentially similar performance.
There also is an unmet need for an accurate, linear pipeline ADC which avoids problems associated with pipeline ADCs that utilize reference scaling.
There also is an unmet need for a technique for reducing the difficulty of designing the components of a high-resolution pipeline ADC.